1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to a MOS semiconductor device having a trench gate structure.
2. Description of the Related Art
FIGS. 6 and 7 illustrate an exemplary conventional vertical MOSFET having a trench gate structure (hereinafter referred to as “trench MOSFET”). FIG. 6 is a schematic plan view of the trench MOSFET and its circumference. FIG. 7 is a schematic cross-sectional view taken along the line C-C′ of FIG. 6.
As illustrated in FIGS. 6 and 7, a P-type well layer 2 and a P-type body layer 3 are formed in a surface layer part of a semiconductor substrate 1 in a cell circumferential region 16 and a cell region 15, respectively, and an N-type source region 9 is formed in a surface layer part of the P-type body layer 3. A trench 4 is formed at such a depth that the trench 4 passes through the source region 9 and the body layer 3. On an inner wall of the trench 4, a gate insulating film 5 such as silicon dioxide and a gate electrode 6 such as polysilicon are formed in this order, to thereby constitute a trench gate. At the outermost circumference of the trench gate, a gate lead wiring 7 such as polysilicon is formed from a region on the gate electrode 6 to a region on a field insulating film 13 such as silicon dioxide formed in a surface layer part of the P-type well layer 2, and the gate lead wiring 7 is electrically connected to the gate electrode 6. In this case, the width of the trench 4 at the outermost circumference is larger than the width of other trenches in order to electrically connect the gate electrode 6 and the gate lead wiring 7 to each other. The gate lead wiring 7 is further electrically connected to a gate wiring 10 such as aluminum via a gate contact hole 8 that is provided above the field insulating film 13 so as to pass through an interlayer insulating film 14 formed on the gate lead wiring 7. In the vicinity of the cell region 15, the interlayer insulating film 14 is formed so as to cover on the trench gate, and a source wiring 11 such as aluminum is formed thereon so that the source region 9 and the source wiring 11 are electrically connected to each other. A drain electrode 12 is formed on a rear surface of the substrate 1, thereby forming a vertical element structure.
As illustrated in FIGS. 6 and 7, Japanese Patent Application Laid-open No. 2009-188294 discloses the structure in which the outermost circumferential trench gate of the trench MOSFET is formed into an annular shape, and the gate lead wiring 7 is formed to extend toward the cell circumferential region 16 so that one end thereof is connected to the electrode 6 in an overlapping manner, thereby decreasing the gate resistance.
In FIG. 7, however, the gate lead wiring 7 is formed also on a corner made up of a side surface of the trench 4 and a front surface of the substrate 1. In the case where the gate insulating film 5 is formed by thermal oxidation of silicon, because the gate insulating film 5 is liable to be thin at the corner, there is a problem of an increased gate leakage current between the gate electrode 6 and the P-type well layer 2 or a decreased gate breakdown voltage.